← Back to Publications List

Process Voltage Temperature Performance Comparison of CMOS and GDI Based Arithmetic Circuits in 45 nm and 180 nm Technologies

Students & Supervisors

Student Authors
Sadia Tasnim Shara
Bachelor of Science in Electrical & Electronic Engineering, FE
Hamim Ibrahim
Bachelor of Science in Electrical & Electronic Engineering, FE
Supervisors
Md. Mortuza Ahmmed
Associate Professor, Faculty, FST

Abstract

Nowadays, maintaining dependable and energy effi- cient digital performance is getting harder under Process, Volt- age, and Temperature (PVT) variations as technology nodes get smaller and circuits get more crowded. Three popular arithmetic circuits a 2-to-1 multiplexer, a 2-bit comparator, and a full adder are designed with both CMOS and Gate Diffusion Input (GDI) logic styles across 45 nm and 180 nm nodes and they are compared in this paper. Cadence Virtuoso post layout simulations were performed under realistic PVT corners (-40°C to 125°C), examining average power, area, transistor count, propagation delay, and leakage power. The findings demonstrated that 180 nm GDI circuits offered comparatively lower power consumption. leakage, and improved thermal stability which made them more appropriate for low power, reliable embedded systems, even though 45 nm CMOS circuits produced faster speeds. Without sacrificing functional reliability, these findings offer engineers useful design insights for energy conscious VLSI applications.

Keywords

Comparator Logic GDI Temperature 180nm technology

Publication Details

  • Type of Publication:
  • Conference Name: 28th International Conference on Computer and Information Technology (ICCIT)
  • Date of Conference: 19/12/2025 - 19/12/2025
  • Venue: Long Beach Hotel
  • Organizer: IEEE Bangladesh Section
View on Publisher